This invention relates to an integrated circuit device and more particularly to an integrated circuit device suited for a gate array which allows diagnosis tests to be easily performed.
It is required in a semiconductor integrated circuit (hereinafter referred to as LSI) to attain a high fault-coverage close to 100% using a test pattern in order to increase its mass-productivity and reliability.
Test pattern input signals are externally applied to a semiconductor circuit device including logic circuits in order to judge if several logic elements included in the device provide desired functions and characteristics. This process is generally called a "diagnosis". Here, the input test patterns used must be ones enabling an exhaustive diagnosis of the internal logic elements. The ratio of the number of diagnosable elements relative to the total number of elements is defined as stuck-fault coverage ratio. Therefore, these input test patterns must be made so that the coverage ratio suited for actual use may be attained with the number of the steps being as small as possible. Common logic integrated circuit devices, however, generally require thousands of steps for actual use, and further with the development of higher integration device in recent years, tens of thousands of steps are required to provide the coverage ratio close to 100%. Therefore, the realization of satisfactory coverage ratios has become difficult.
Thus, integration degrees as high as thousands to ten thousands of gates makes it almost impossible to boost the coverage ratio by using only the test patterns, and requires some test circuit to be provided. The provision of the test circuit may result in a large scale for the entire circuit, which will reduce the effective integration degree. This is remarkable in a gate array LSI which has a predetermined number of gates on the entire chip (In the case of a customized LSI, the reduction of integration density can be minimized in some degree through the optimization of transistor size and cell arrangement). Incidentally, the term "gate array LSI" means an LSI in which only a few masks corresponding to wirings, among dozen or so of the masks used in the fabrication of the LSI, are made in accordance with the logical specifications to be developed to provide a desired electric circuit operation. In the gate array LSI, the wafers, which have been through the majority of the steps prior to the wiring steps, are previously stocked. Therefore, the turnaround time of development and fabrication cost can be greatly reduced.
These input test patterns have hitherto been manually made, which demands a very large amount of labor. Particularly, the gate array LSI, in which the most of designing operations are automated and the period of designing is shortened to one month or so, necessarily takes an increased amount of time to make the input test patterns. The long period of time-required for designing the test patterns provides one of the greatest obstacles in shortening the development period.
Thus, there has been proposed, as in U.S. patent application Ser. No. 575,706 filed on Jan. 31, 1984, now U.S. Pat. No. 4,613,970 issued 9/23/86 a partitioning diagnosis system which performs a scan-in and scan-out of test data using a dedicated test data bus. In this case, normal operation pins and test pins in the gate array are shared so that an increased number of parallel input/output pins for scan-in/out can be used. Thus, the number of the steps of the test patterns is reduced.
Here, the partitioning diagnosis is defined as a diagnosis in which an entire circuit, on the basis of logic connection information, is partitioned into groups of sequential circuits, which have a storage function of data, and groups of combinational circuits intervening therebetween which definitely determine outputs from determined inputs. This method replaces the diagnosis of the entire circuit by a diagnosis of only the combinational circuit groups in which a coverage ratio close to 100% is theoretically possible.
An example of the circuit arrangement after the partition is shown in FIG. 10. In this example, the circuits are divided into three parts. More specifically, all of the combinational circuits are divided into groups of combinational circuits 4, 5, and 6, intervened by groups of sequential circuits 1, 2, and 3. In FIG. 10, numerals 7 designate bonding pads; 8-1, 8-2, 8-3 are test data write signal lines for the individual sequential circuits groups 1 to 3, respectively; 9-1, 9-2, 9-3 are test data read signal lines for the individual sequential circuit groups 1 to 3, respectively; 16-1, 16-2, 16-3 are input control signal lines for inhibiting the input of the normal data into the sequential circuits groups 1 to 3, respectively; 10 to 15, and 18 are wirings between the sequential circuit groups 1 to 3 and the combinational circuit groups 4 to 6, which are determined by logic design; and 17-1, 17-2, 17-3 are test data bus lines dedicated to diagnosis, which transfer the test data.
The operation of the test circuits for partitioning diagnosis will be explained below. First, the case will be considered where the combinational circuits 5 are tested. In the test mode, first, with the input control signals on the lines 16-1, 16-2, and 16-3 set to a "0" level, i.e., a LOW logic level (when these signals are set to a HIGH LEVEL, the system is in the normal logic mode), the supply of the signals on the lines 10, 12 and 14 into the combinational circuits groups 1, 2 and 3, respectively is inhibited. Next, with the write signal on the line 8-2 set to the "1" level for a certain time with a certain pulse interval, test data (or test patterns) are written into the sequential circuit group 2 through the bus line 17-2. Thus, the setting of the test patterns for the combinational circuit group 5 has been completed. Next, in a normal logic mode, with the input control signal on the line 16-3 set to the "1" level for a certain time, outputs from the combinational circuit group 5, i.e., signals on the lines 14 are set into the sequential circuit group 3. The test data, written into the sequential circuit group 3, are outputted to the test data bus line 17-3 by setting the read signal on the line 9-3 to the "1" level for a certain time. Thus, the scan-in, scan-out operation of one step of the input test patterns has been completed. The above operation is repeated according to the number of steps of the test patterns to test the combinational circuit group 5 until the test coverage ratio thereof reaches 100% or the neighborhood thereof. Subsequently, the diagnosis of the combinational circuit groups 4 and 6 is also made in the same manner. Incidentally, in the example mentioned above, for the sake of simplicity, each of the sequential circuit groups is illustrated to have only one write signal line, one read signal line and one data bus line, but in effect, the individual combinational circuits included in the combinational circuit groups have plural addressing systems and so each of the above lines is composed of plural number.
In this way, in the case of diagnosis of the combinational circuit group 5, with the test patterns set in the sequential circuit group 2, the outputs from the combinational circuit group 5 are read out using the sequential circuit group 3, and after the completion of diagnosis operations for the combinational circuit group 5, the diagnosis operations for the combinational circuit group 4 will be performed. In order to test this combinational circuit group 4, with the test patterns set into the sequential circuit group 1, the outputs from the combinational circuit group 4 is read out using the sequential circuit group 2. Thus, in the conventional diagnosis system, the above diagnosis operations must be serially repeated many times corresponding to the number of divisions, which results in a very large number of test steps. Further, there are many test control lines and control signals so that some difficulty will be encountered to apply the conventional diagnosis system to the gate array LSI in which an automatic arrangement and wiring are performed by means of a DA (Design Automation) system. Further, if there are some feedback paths such as shown in FIG. 11, some racing may occur. So, generally this path must be prohibited in the logic design. However, this disadvantageously provides a significant restriction to the logic design in the gate array. In FIG. 11, numeral 20 denotes an edge type flip-flop; 21 is a D-type flip-flop; and 22, 23 are two-input NOR gates. The Q-output from the flip-flop 20 is fed back to the D-input of the flip-flop 20 via a line 24 and the two input NOR gate 22. For the sake of simplicity of illustration, no test control line are shown. In operation, when the test data is set into the flip-flop 20 in the test mode, some racing occurs since the Q-output therefrom is inputted to the D-output. In addition, the property that signals advance unidirectionally from the input side to the output side is not kept, making it impossible to make a partitioning diagnosis.